DocumentCode
866233
Title
A novel CMOS structure with a reduced drain-substrate capacitance
Author
Sagara, Kazuhiko ; Nakamura, Tohru
Author_Institution
Hitachi Ltd., Tokyo, Japan
Volume
36
Issue
3
fYear
1989
fDate
3/1/1989 12:00:00 AM
Firstpage
598
Lastpage
600
Abstract
To implement this structure, lateral diffusion of impurities from the doped polysilicon films to the silicon substrate is used. The fabrication steps are described in detail and the electrical characteristics of the device are summarized. It is shown experimentally that the drain-substrate capacitance is approximately a 0.7 times smaller than that for the conventional CMOS transistor
Keywords
CMOS integrated circuits; capacitance; integrated circuit technology; semiconductor technology; CMOS structure; electrical characteristics; fabrication steps; lateral diffusion of impurities; reduced drain-substrate capacitance; Circuits; Electric variables; Fabrication; Impurities; Parasitic capacitance; Semiconductor films; Silicon; Transistors; Ultra large scale integration; Voltage;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/16.19973
Filename
19973
Link To Document