• DocumentCode
    866398
  • Title

    An automatic netlist-to-schematic generator

  • Author

    Naveen, B. ; Raghunathan, K.S.

  • Author_Institution
    Indian Telephone Ind. Ltd., Bangalore, India
  • Volume
    10
  • Issue
    1
  • fYear
    1993
  • fDate
    3/1/1993 12:00:00 AM
  • Firstpage
    36
  • Lastpage
    41
  • Abstract
    The N2S schematic generator, which uses a variable-ordering technique in the initial placement phase and simple heuristics in the final placement phase, is described. Its channel-routing techniques result in signal routing with minimal crossovers. The authors demonstrate the efficiency of N2S by applying it to a set of benchmark sequential circuits.<>
  • Keywords
    VLSI; circuit layout CAD; logic CAD; sequential circuits; N2S schematic generator; VLSI; automatic netlist-to-schematic generator; benchmark sequential circuits; channel-routing; heuristics; initial placement phase; signal routing; variable-ordering technique; Circuit synthesis; Design automation; Design methodology; Documentation; Process design; Routing; Sequential circuits; Signal synthesis; Silicon compiler; Telephony;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.199803
  • Filename
    199803
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=866398