Integrated complementary transistor nanosecond logic

An integrated complementary transistor circuit family particularly suited to high-speed system applications is described. Delays per logic decision ranging from three to six nanoseconds are common with associated rise times ranging from 5 to 15 nsec. This has been accomplished by designing the circuits in conjunction with system interconnection considerations. The basic circuit types are p-n-p--n-p-n AND-OR gate and a compatible NOR-OR gate. The AND-OR gate is comparable to a diode AND-OR gate but with current gain added, thus improving the fan-in and fan-out characteristics. The faster functional operation with slower rise times is based on minimum delay through the emitter follower type AND-OR gate. The resulting wired-OR function allows additional logical flexibility. Typically, three or four levels of AND-OR circuitry may be used before the voltage levels need be restored. The NOR-OR element completes the basic logic complement, establishes the basic rise time of the circuits, restores the voltage levels, and provides noise rejection. The rise time is selected to allow open wire signal lines for all but the longest interconnections. The static and dynamic characteristics of these circuits are presented in detail. Effects of capacitive loading, fan-out, and isolation capacitance are described. Noise rejection is discussed along with various modes of noise generation. Functional performance of the circuit family is demonstrated with two subsystem functions. A fifty-gate fast-carry pyramid was constructed using open transmission lines to study small function operations. Noise and delay characteristics are given. Register-to-register communication over a five-register bus was demonstrated with a 150-gate model.