Title :
Logic p.r.b.s. delay calculator and delayed-version generator with automatic delay-changing facility
Author_Institution :
University of Strathclyde, Electrical Engineering Department, Glasgow, UK
fDate :
7/1/1965 12:00:00 AM
Abstract :
A logic technique for determining the modulo 2 additions necessary to generate any given delay of a pseudorandom binary sequence is described. If the modulo 2 additions are carried out by an odd/even test, it is shown how the delay calculator can be used to automatically change the delay of the delayed version being generated.
Keywords :
calculation; delay circuits;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19650115
