A circuit-design approach for enhancing the yield of complex iterative integrated electronic subsystems

Since the preselection of individual components is impossible in integrated electronics, component parameters are, in general, characterized by nontruncated probability density functions which reflect the accuracy of the manufacturing process. The significant thermal resistance in practical integrated electronic sub-systems causes temperature gradients which further increase the effective standard deviation of component parameter probability density functions. As ever increasing numbers of components are constrained to ever decreasing volume, the temperature gradient can cause profound effects including the seeming paradox of a decrease in subsystem yield with increasing design range in parameter values. This paper proposes a straightforward and flexible approach, primarily applicable to digital circuits, which results in a circuit design which is directly related to the functional performance requirements, the accuracy of the manufacturing process, the thermal characteristics of the packaging scheme, and which results in a subsystem with enhanced probability of functioning correctly when fabricated. The approach can make use of any valid "worst-case" design procedures presently available for given topologies provided that the "worst-case" limits are picked in a specific unusual way which is described.