An Experimental Perspective of Trap Generation Under BTI Stress

Author

Mukhopadhyay, Subhadeep ; Mahapatra, Souvik

Author_Institution

Dept. of Electr. Eng., IIT Bombay, Mumbai, India

Volume

62

Issue

7

fYear

2015

fDate

Jul-15

Firstpage

2092

Lastpage

2097

Abstract

A gated-diode or direct current IV method is used to characterize trap generation (TG) under negative-bias temperature instability (NBTI) and positive-bias temperature instability (PBTI) stress in different planar high-k metal gate p-channel and n-channel MOSFETs, respectively. After correction of the measurement delay, very similar time (tSTR), voltage (VG,STR), temperature (T), AC pulse duty cycle, and frequency ( f ) dependence of TG is seen for NBTI and PBTI. Measured TG shows power-law time dependence with a time exponent of n ~ 0.16 for NBTI and PBTI and for DC and AC stress. Uncoupled nature of voltage acceleration (Γ) and T activation (EA) is seen. Interlayer scaling has a similar impact on EA and Γ for NBTI and PBTI. However, the physical location of TG is shown to be different for NBTI and PBTI stress.

Keywords

MOSFET; electron traps; hole traps; negative bias temperature instability; semiconductor device reliability; AC stress; BTI stress; DC stress; NBTI; PBTI; direct current IV method; gated diode; negative bias temperature instability; planar high-K metal gate MOSFET; positive bias temperature instability; trap generation; voltage acceleration; Delays; High K dielectric materials; Logic gates; Stress; Stress measurement; Temperature measurement; Direct current IV (DCIV); high- $k$ metal gate (HKMG); high-k metal gate (HKMG); interlayer (IL) scaling; negative-bias temperature instability (NBTI); positive-bias temperature instability (PBTI); trap generation (TG); trap generation (TG).;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2015.2434955

Filename

7116557