Title :
Transforming Cyclic Circuits Into Acyclic Equivalents
Author :
Neiroukh, Osama ; Edwards, Stephen A. ; Song, Xiaoyu
Author_Institution :
Intel Corp., Hillsboro, OR
Abstract :
Designers and high-level synthesis tools can introduce unwanted cycles in digital circuits, and for certain combinational functions, cyclic circuits that are stable and do not hold state are the smallest or most natural representations. Cyclic combinational circuits have well-defined functional behavior yet wreak havoc with most logic synthesis and timing tools, which require combinational logic to be acyclic. As such, some sort of cycle-removal step is necessary to handle these circuits with existing tools. We present a two-stage algorithm for transforming a combinational cyclic circuit into an equivalent acyclic circuit. The first part quickly and exactly characterizes all combinational behavior of a cyclic circuit. It starts by applying input patterns to each input and examining the boundary between gates whose outputs are and are not defined to find additional input patterns that make the circuit behave combinationally. It produces sets of assignments to inputs that together cover all combinational behavior. This can be used to report errors, as an optimization aid, or to restructure the circuit into an acyclic equivalent. The second stage of our algorithm does this restructuring by creating an acyclic circuit fragment from each of these assignments and assembles these fragments into an acyclic circuit that reproduces all the combinational behavior of the original cyclic circuit. Experiments show that our algorithm runs in seconds on real-life cyclic circuits, making it useful in practice.
Keywords :
combinational circuits; equivalent circuits; high level synthesis; combinational logic; cycle-removal step; cyclic circuits; cyclic combinational circuits; digital circuits; equivalent acyclic circuit; high-level synthesis tools; Assembly; Circuit analysis computing; Circuit simulation; Circuit synthesis; Combinational circuits; Digital circuits; High level synthesis; Logic circuits; Logic gates; Timing; Acyclic circuits; combinational logic; constructiveness; cyclic circuits; resynthesis;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2008.2003305