Circuit-Level Impact of a-Si:H Thin-Film-Transistor Degradation Effects

Author

Allee, David R. ; Clark, Lawrence T. ; Vogt, Bryan D. ; Shringarpure, Rahul ; Venugopal, Sameer M. ; Uppili, Shrinivas Gopalan ; Kaftanoglu, Korhan ; Shivalingaiah, Hemanth ; Li, Zi P. ; Fernando, J. J Ravindra ; Bawolek, Edward J. ; O´Rourke, Shawn M.

Author_Institution

Flexible Display Center, Arizona State Univ., Tempe, AZ

Volume

56

Issue

6

fYear

2009

fDate

6/1/2009 12:00:00 AM

Firstpage

1166

Lastpage

1176

Abstract

This paper reviews amorphous silicon thin-film-transistor (TFT) degradation with electrical stress, examining the implications for various types of circuitry. Experimental measurements on active-matrix backplanes, integrated a-Si:H column drivers, and a-Si:H digital circuitry are performed. Circuit modeling that enables the prediction of complex-circuit degradation is described. The similarity of degradation in amorphous silicon to negative bias temperature instability in crystalline PMOS FETs is discussed as well as approaches in reducing the TFT degradation effects. Experimental electrical-stress-induced degradation results in controlled humidity environments are also presented.

Keywords

MOSFET; driver circuits; thin film transistors; active-matrix backplanes; amorphous silicon thin-film-transistor degradation; circuit modeling; circuit-level impact; column drivers; complex-circuit degradation; crystalline PMOS FET; digital circuitry; electrical-stress-induced degradation; negative bias temperature instability; Active matrix technology; Amorphous silicon; Backplanes; Degradation; Driver circuits; Integrated circuit measurements; Performance evaluation; Predictive models; Stress; Thin film transistors; Amorphous silicon; flexible electronics; thin-film transistors (TFTs); threshold-voltage shift;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2009.2019387

Filename

4926162