Title :
44.6% processing cycles reduction in GSM voice coding by low-power reconfigurable co-processor architecture
Author :
Atzori, E. ; Carta, S.M. ; Raffo, L.
Author_Institution :
Dept. of Electr. & Electron. Eng., Cagliari Univ., Italy
fDate :
11/21/2002 12:00:00 AM
Abstract :
A reconfigurable architecture oriented to low-power digital signal processing is presented, synthesised and tested on ETSI-GSM voice coding algorithms. An overall reduction of 44.6% cycles with respect to standard RISC processors is obtained. Such improvement together with locality and temporal correlation allows a reduction of power consumption.
Keywords :
cellular radio; coprocessors; digital signal processing chips; low-power electronics; reconfigurable architectures; speech coding; telecommunication computing; ETSI-GSM voice coding algorithm; digital signal processing; low-power reconfigurable co-processor architecture; mobile communication system;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20021019
