High Performance Architecture of an Application Specific Processor for the H.264 Deblocking Filter

Author

Dang, Philip

Author_Institution

STMicroelectronics, Inc., La Jolla, CA

Volume

16

Issue

10

fYear

2008

Firstpage

1321

Lastpage

1334

Abstract

This paper presents an efficient architecture of an application specific processor (ASP) designed for the deblocking filter algorithm of the H.264 video compression standard. Several optimization techniques at different design levels, such as vector register, pipeline processing, very long instruction word (VLIW) processor, and predication, are utilized in this design. The proposed ASP can meet the real time constraint of the deblocking filter algorithm for the 16:9 video format (4690 times 2304) at 30 frames per second (fps) at 200-MHz clock rate.

Keywords

application specific integrated circuits; data compression; filters; microprocessor chips; video coding; H.264 deblocking filter; H.264 video compression; application specific processor; deblocking filter algorithm; pipeline processing; vector register; very long instruction word processor; Algorithm design and analysis; Application specific processors; Clocks; Design optimization; Filters; Pipeline processing; Process design; Registers; VLIW; Video compression; Application specific processor (ASP); H.264; VLSI architecture; deblocking filter; video compression;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2008.2002683

Filename

4629344