On network partitioning algorithm of large-scale CMOS circuits

A topological partitioning algorithm which decouples the large-scale CMOS circuits into numerous small-scale subcircuits, in which each subcircuit can be individually analyzed with better overall efficiency, is discussed. The parasitic couplings between the partitioned subcircuits are shown to be negligible in most digital circuits. Bidirectional coupling between cross-coupled subcircuits is studied and a decoupling criterion is derived. The flexibility offered by the decoupled structure can be fully taken advantage of by using: (1) the latency; (2) the event-driven operation; and (3) the regular structure of the partitioned subcircuits. An experimental program, as a result from the partitioning algorithm, demonstrates a three-order-of-magnitude speed improvement over the SPICE program