Design of an efficient VLSI inner-product processor for real-time DSP applications

A technique for the design of an efficient word-level inner-product processor based on a parallel array multiplier is described. This processor cell forms the fundamental computing module of the systolic array architectures that are increasingly used to solve many computationally intensive DSP functions. These functions are characterized by linear recurrences involving multiply-add/subtract operations. The use of the present scheme results in the total elimination of the separate-adder module that is usually required along with a multiplier unit in conventional designs. Simulation results of a linear bidirectional systolic array are presented for a test-case example of a convolution problem. A reduction of 32-50% in the computation time is achieved. Besides, it results in reducing the number of basic cells used, making it highly attractive for VLSI implementation.