DocumentCode
869663
Title
All digital phase-locked loop: concepts, design and applications
Author
Shayan, Y.R. ; Le-Ngoc, T.
Author_Institution
Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
Volume
136
Issue
1
fYear
1989
fDate
2/1/1989 12:00:00 AM
Firstpage
53
Lastpage
56
Abstract
The concepts of an all digital phase-locked loop (DPLL), which contains a purely digital phase detector, loop filter and voltage-controlled oscillator, are explained. A second order DPLL is considered and analysed using the Z-transform technique. Implementation of the DPLL, based on the CMOS digital signal processor TMS 320C25, and the experimental results, are presented. Potential applications are also discussed.
Keywords
CMOS integrated circuits; digital signal processing chips; phase-locked loops; CMOS digital signal processor; TMS 320C25; Z-transform; digital phase detector; digital phase-locked loop; loop filter; second order DPLL; voltage-controlled oscillator;
fLanguage
English
Journal_Title
Radar and Signal Processing, IEE Proceedings F
Publisher
iet
ISSN
0956-375X
Type
jour
Filename
20236
Link To Document