DocumentCode
869695
Title
Test generation for pattern-sensitive faults in integrated switches
Author
Tyszer, Jerzy
Author_Institution
Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
Volume
39
Issue
11
fYear
1991
fDate
11/1/1991 12:00:00 AM
Firstpage
1546
Lastpage
1548
Abstract
The problem of pattern-sensitive fault detection in integrated time-division switches is discussed. It is shown that high fault coverage can be obtained by applying random test vectors produced by a maximum-length linear feedback shift register. Two tester architecture solutions are proposed
Keywords
digital integrated circuits; fault location; integrated circuit testing; shift registers; switching circuits; time division multiplexing; high fault coverage; integrated circuit testing; integrated time-division switches; linear feedback shift register; pattern-sensitive fault detection; random test vectors; test generation; time division multiplexing; Circuit faults; Circuit testing; Communication switching; Fault detection; Linear feedback shift registers; Random access memory; Switches; Telecommunication control; Telecommunication switching; Test pattern generators;
fLanguage
English
Journal_Title
Communications, IEEE Transactions on
Publisher
ieee
ISSN
0090-6778
Type
jour
DOI
10.1109/26.111431
Filename
111431
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