Title :
Test generation for pattern-sensitive faults in integrated switches
Author_Institution :
Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada
fDate :
11/1/1991 12:00:00 AM
Abstract :
The problem of pattern-sensitive fault detection in integrated time-division switches is discussed. It is shown that high fault coverage can be obtained by applying random test vectors produced by a maximum-length linear feedback shift register. Two tester architecture solutions are proposed
Keywords :
digital integrated circuits; fault location; integrated circuit testing; shift registers; switching circuits; time division multiplexing; high fault coverage; integrated circuit testing; integrated time-division switches; linear feedback shift register; pattern-sensitive fault detection; random test vectors; test generation; time division multiplexing; Circuit faults; Circuit testing; Communication switching; Fault detection; Linear feedback shift registers; Random access memory; Switches; Telecommunication control; Telecommunication switching; Test pattern generators;
Journal_Title :
Communications, IEEE Transactions on
