Variability reduction in CMOS operational amplifiers through layout modification

A variability analysis for a CMOS operational amplifier has been performed by a technique based on the sensitivity information of the performance parameters with respect to the process-component parameters. The variability of the offset voltage has been computed with respect to the threshold voltage. Three-level statistical data of the threshold voltage have been obtained for use in the variability computations. Based on the sensitivity analysis, an improved layout has been prepared to reduce variability by matching the components having opposite sensitivities, some of which are seemingly unrelated. The CMOS operational amplifier has been fabricated with both the basic and proposed layouts in p-well, Si-gate technology with a 5 mu m design rule. Experimentally observed statistical data for the offset voltage show a reduction in variability with the proposed layout as predicted by theoretical computations.