DocumentCode
869876
Title
Propagating SET Characterization Technique for Digital CMOS Libraries
Author
Baze, M.P. ; Wert, J. ; Clement, J.W. ; Hubert, M.G. ; Witulski, A. ; Amusan, O.A. ; Massengill, L. ; McMorrow, D.
Author_Institution
Boeing Co., Seattle, WA
Volume
53
Issue
6
fYear
2006
Firstpage
3472
Lastpage
3478
Abstract
A circuit architecture based on simple logic gates is described which uses small chip areas and low speed testing to characterize single event transients for digital applications. Utility of this architecture is demonstrated with heavy ion data on a 130 nm library
Keywords
CMOS logic circuits; combinational circuits; integrated circuit testing; logic gates; radiation hardening (electronics); transients; 130 nm; LET; SET propagation; circuit architecture; combinational logic; digital CMOS libraries; heavy ion data; linear energy transfer; logic gates; low speed testing; single event transients propagation; CMOS digital integrated circuits; CMOS logic circuits; CMOS technology; Circuit testing; Logic devices; Logic testing; Pulse shaping methods; Shape; Software libraries; Space vector pulse width modulation; Asynchronous; combinational logic; dissipation; linear energy transfer (LET); propagation; single event transient (SET);
fLanguage
English
Journal_Title
Nuclear Science, IEEE Transactions on
Publisher
ieee
ISSN
0018-9499
Type
jour
DOI
10.1109/TNS.2006.884969
Filename
4033208
Link To Document