• DocumentCode
    870309
  • Title

    An analytical back-gate bias effect model for ultrathin SOI CMOS devices

  • Author

    Sim, Jai-hoon ; Kuo, James B.

  • Author_Institution
    Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
  • Volume
    40
  • Issue
    4
  • fYear
    1993
  • fDate
    4/1/1993 12:00:00 AM
  • Firstpage
    755
  • Lastpage
    765
  • Abstract
    An analytical back-gate bias effect model for ultrathin SOI CMOS devices is presented. As verified by PISCES results, the analytical SOI CMOS back-gate bias effect model provides a much better accuracy in the integral potential distribution and the threshold voltage as the back-gate bias is changed
  • Keywords
    CMOS integrated circuits; semiconductor device models; semiconductor-insulator boundaries; PISCES results; analytical model; back-gate bias effect model; integral potential distribution; threshold voltage; ultrathin SOI CMOS devices; Capacitance; Electrostatics; Insulation; MOS devices; Semiconductor device modeling; Semiconductor films; Silicon; Substrates; Thin film devices; Voltage;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/16.202788
  • Filename
    202788
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=870309