Digital Device Error Rate Trends in Advanced CMOS Technologies

Author

Gadlage, Matthew J. ; Eaton, Paul H. ; Benedetto, Joseph M. ; Carts, Marty ; Zhu, Vivian ; Turflinger, Thomas L.

Author_Institution

NAVSEA Crane, IN

Volume

53

Issue

6

fYear

2006

Firstpage

3466

Lastpage

3471

Abstract

In this paper, data are presented from test chips in four technology nodes. With this data, the trends in single event effects as feature sizes shrink are studied. Some of the trends discussed include upset thresholds, shrinking cross sections, multiple bit upsets, and per bit error rate trends. Also included in this paper is some of the first ever heavy ion data from a 65 nm CMOS technology. With data from the 250 nm, 180 nm, 90 nm, and 65 nm technology nodes, the past, present, and future of what the radiation effects community has dealt with and will be dealing with when it comes to single event effects is presented

Keywords

CMOS digital integrated circuits; error statistics; integrated circuit technology; integrated circuit testing; ion beam effects; radiation hardening (electronics); 180 nm; 250 nm; 65 nm; 90 nm; CMOS technology; digital device error rate trends; heavy ion data; ion radiation effects; multiple bit upsets; shrinking cross sections; single event effects; test chips; upset thresholds; Bit error rate; CMOS technology; Circuit testing; Cranes; Error analysis; Flip-flops; Radiation effects; Single event upset; Space charge; Space technology; Heavy ion; ion radiation effects; single-event upset (SEU);

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2006.886212

Filename

4033480