An Area and Power Efficient Radiation Hardened by Design Flip-Flop

Author

Knudsen, Jonathan E. ; Clark, Lawrence T.

Author_Institution

Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ

Volume

53

Issue

6

fYear

2006

Firstpage

3392

Lastpage

3399

Abstract

A radiation hardened by design flip-flop with high single event effect immunity is described. Circuit size and power are reduced by a combination of proven SEE hard techniques, i.e., a temporal latch master and DICE slave are used. Two shift register chains each comprised of 1920 flip-flops have been implemented in the IBM 0.13 mum bulk CMOS process. Measured SEE immunity in accelerated heavy ion testing, and power results are described. A threshold LET over 45 LET (MeV-cm²/mg) at V_DD=1.5 V is demonstrated. High layout density and the likely high LET failure mechanisms are described

Keywords

CMOS logic circuits; flip-flops; integrated circuit design; radiation hardening (electronics); sequential circuits; shift registers; 0.13 micron; DICE slave; IBM; SEE hard techniques; accelerated heavy ion testing; bulk CMOS process; circuit power; circuit size; flip-flop; high LET failure mechanisms; high layout density; high single event effect immunity; power efficient radiation hardening design; sequential logic circuits; shift register chains; single event transients; temporal latch master; CMOS process; Circuits; Failure analysis; Flip-flops; Latches; Life estimation; Master-slave; Power measurement; Radiation hardening; Shift registers; Flip-flop; radiation hardened by design; sequential logic circuits; single event effects; single event transients;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2006.886199

Filename

4033595