Small chips in crossed wires

Could the next generation in semiconductor process technology be undermined by the legacy of unresolved technical problems? As we enter 2004, the next phase in integrated circuit manufacturing will begin in earnest, with companies starting to ramp up production of chips based on the 90 nm process. But bad experiences with the 130 nm process, which was heavily delayed by manufacturing problems, have made chipmakers cautious. Many companies are holding back from moving to the new process until they see the results that the more optimistic chipmakers get. A number of those who have decided to take the plunge early have been careful to keep their options open and trade off die size or speed against manufacturability. Thanks to rapid advances in lithography-the photographic processes used to create tiny features on chips-transistors have shrunk more quickly than was expected in the late 1990s. These gains have not been reflected in other chip-level features. Chipmakers have faced increasing problems scaling down the wires that join transistors together. To maintain an effective doubling in density between generations, the distance between the wires and their lateral thickness has to reduce by about 30%. Unfortunately as the wires get closer together, interference between signals on adjacent wires becomes harder and harder to overcome.