Title :
On the exploration of the solution space in analog placement with symmetry constraints
Author :
Balasa, Florin ; Maruvada, Sarat C. ; Krishnamoorthy, Karthik
Author_Institution :
Dept. of Comput. Sci., Univ. of Illinois, Chicago, IL, USA
Abstract :
The traditional way of approaching placement problems in computer-aided design (CAD) tools for analog layout is to explore an extremely large search space of feasible or unfeasible placement configurations, where the cells are moved in the chip plane (being even allowed to overlap in possibly illegal ways) by a stochastic optimizer. This paper presents a novel exploration technique for analog placement operating on a subset of tree representations of the layout-called symmetric-feasible, where the typical presence of an arbitrary number of symmetry groups of devices is directly taken into account during the search of the solution space. The computation times exhibited by this novel approach are significantly better than those of the algorithms using the traditional exploration strategy. This superior efficiency is partly due to the use of segment trees, a data structure introduced by Bentley, mainly used in computational geometry.
Keywords :
analogue integrated circuits; circuit layout CAD; computational geometry; integrated circuit layout; network topology; sequences; symmetry; trees (mathematics); B*-tree; CAD tools; O-tree; analog layout; analog placement; chip plane; computational geometry; computer-aided design; exploration technique; large search space; placement configurations; placement problems; sequence-pair; solution space; stochastic optimizer; symmetric-feasible; symmetry constraints; topological representations; Analog circuits; Circuit noise; Constraint optimization; Cost function; Coupling circuits; Crosstalk; Design automation; Design optimization; Noise shaping; Stochastic processes;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2003.822132