Wafer-level testing with a membrane probe

Author

Leslie, Brian ; Matta, Farid

Author_Institution

Hewlett-Packard Lab., Palo Alto, CA, USA

Volume

6

Issue

1

fYear

1989

Firstpage

10

Lastpage

17

Abstract

The authors describe a proprietary membrane probe card that addresses the needs of testing VLSI devices at the wafer level. The membrane probe allows the testing of devices with a high pin count at operating speed, while allowing a complete package test at the wafer level. The concepts and structure of the probe are examined, and its performance is demonstrated by time-domain and frequency-domain measurements of the typical electrical characteristics of a VLSI digital probe that accesses 272 pads at a pitch of 110 mu m. Applications to a bipolar ECL (emitter-coupled logic) flash A/D (analog-to-digital) converter, a bipolar ECL D/A converter, an application-specific CMOS IC, an NMOS VLSI central processing unit, and area-array solder bumps are presented.<>

Keywords

CMOS integrated circuits; VLSI; analogue-digital conversion; digital-analogue conversion; integrated circuit testing; probes; NMOS VLSI central processing unit; VLSI devices; application-specific CMOS IC; area-array solder bumps; bipolar ECL A/D convertor; bipolar ECL D/A converter; complete package test; frequency-domain measurements; membrane probe; time domain measurements; wafer level testing; Analog-digital conversion; Biomembranes; Electric variables measurement; Frequency measurement; Packaging; Probes; Testing; Time domain analysis; Very large scale integration; Wafer scale integration;

fLanguage

English

Journal_Title

Design & Test of Computers, IEEE

Publisher

ieee

ISSN

0740-7475

Type

jour

DOI

10.1109/54.20385

Filename

20385