Post-layout verification of the WE DSP32 digital signal processor

Author

Bays, Laurence E. ; Chen, Chin-Fu ; Fields, Evelyn M. ; Gadenz, Renato N. ; Hays, W. Patrick ; Moscovitz, Howard S. ; Szymanski, Thomas G.

Author_Institution

AT&T Bell Lab., Holmdel, NJ, USA

Volume

6

Issue

1

fYear

1989

Firstpage

56

Lastpage

66

Abstract

The authors describe the successful postlayout verification of the WE DSP32 digital signal processor and the application of advanced CAD (computer-aided design) tools. The development work culminated in the smooth transfer of the DSP32 design into high-volume production. During this period, the authors were able to diagnose and repair hundreds of design errors. They also caught errors in the test-vector software and fixed them before first silicon. They estimate that their verification work saved the DSP32 project a year of silicon debugging. In addition, the authors were able to enhance the CAD tools themselves.<>

Keywords

CAD; digital signal processing chips; CAD tools; WE DSP32 digital signal processor; design errors; post layout verification; silicon debugging; test-vector software; Application software; Application specific integrated circuits; Circuit synthesis; Circuit testing; Databases; Design automation; Digital signal processors; Production; Silicon; Software testing;

fLanguage

English

Journal_Title

Design & Test of Computers, IEEE

Publisher

ieee

ISSN

0740-7475

Type

jour

DOI

10.1109/54.20390

Filename

20390