Hardness Assurance Statistical Methodology for Semiconductor Devices

A statistical method is developed for determining electrical end-point limits for semiconductor devices subjected to radiation stress. The approach utilizes multiple lot radiation data and can be applied where lot-to-lot variations in radiation response are large compared to variations within a lot. Such limits may be used as design parameter limits or as failure limits for lot acceptance testing of future hardness-assured, semiconductor production lots. The method was applied for neutron and total gamma dose effects on low power bipolar transistors, digital TTL ICs, and a power transistor for which an adequate multiple-lot radiation database existed.