Title :
Considerations for Single Event Immune VLSI Logic
Author :
Diehl, S.E. ; Vinson, J.E. ; Shafer, B.D. ; Mnich, T.M.
Author_Institution :
North Carolina State University Electrical and Computer Engineering Department P. O. Box 5275, Raleigh, North Carolina 27650
Keywords :
CMOS logic circuits; CMOS process; Computer errors; Laboratories; Latches; Logic arrays; Logic circuits; Random access memory; Very large scale integration; Voltage;
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.1983.4333161
