Novel approaches to the design of VLSI RNS multipliers

Two approaches are proposed for the design of a fast residue number-based multiplier over a Galois field GF(p), where p is a prime number. The first approach uses an isomorphic mapping from the additive index group, modulo (p-1), of GF(p) onto the direct sum of a set of submodular additive groups. The submoduli are selected for minimizing the hardware and increasing the speed. This is accomplished by fully exploiting the properties of a Galois field. The second one uses symmetric residue number arithmetic to perform multiplication. This uses a pseudoprimitive root as the generator for the elements of the multiplicative group of GF(p) and reduces the index storage hardware by 50% and the adder hardware by 1 bit. Multipliers designed with these approaches would be faster and use less silicon area compared to earlier designs reported in the literature