Active compensation of interconnection losses for multi-GHz clock distribution networks

The authors propose an active compensation scheme for losses in heavily loaded high-speed differential clock distribution networks using Si bipolar integrated circuit technology. The compensation network consists of negative impedance converter circuitry and provides performance improvements up to multi-gigahertz frequencies. Even though the compensation technique is proposed in the context of Si bipolar multilevel current switch logic circuits, the analogous application with other high-speed technologies is possible where loading dominates the on-chip transmission line characteristics. The authors give general design guidelines and reports simulation results for a 2-GHz clock distribution example problem using parameters of state-of-the-art single-poly self-aligned Si bipolar transistors