Title :
A fast multilayer general area router for MCM designs
Author :
Khoo, Kei-Yong ; Cong, Jason
Author_Institution :
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
fDate :
11/1/1992 12:00:00 AM
Abstract :
An efficient multi layer general area router is developed as an alternative to the 3-D maze router for solving the multi-layer multichip module (MCM) routing problem. The router, named SLICE, is independent of net ordering, requires much shorter computation time, and uses fewer vias. A key step is to compute a maximum noncrossing bipartite matching, which is solved optimally in O(n log n) time where n is the number of possible connections. The router was tested on a number of examples, including two MCM designs from MCC. The total wirelength used by SLICE is only a few percent away from the optimal on average. Compared with a 3-D maze router, SLICE is six times faster and uses 29% fewer vias. Another feature of SLICE is that it works on only a `thin slice´ of a two-layer routing grid at a time, so it can produce solutions for large MCM routing examples where 3-D maze routers fail due to insufficient memory
Keywords :
circuit layout CAD; multichip modules; network routing; MCM designs; SLICE; maximum noncrossing bipartite matching; multichip module; multilayer general area router; packaging; two-layer routing grid; Delay; Integrated circuit interconnections; Multichip modules; Nonhomogeneous media; Packaging; Routing; Space technology; System performance; Testing; Very large scale integration;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on