DocumentCode
872188
Title
Calculation of steady-state errors in digital-to-analogue ladder convertors
Author
Donaldson, R.W. ; Chan, Daniel
Author_Institution
University of British Columbia, Department of Electrical Engineering, Vancouver, Canada
Volume
3
Issue
5
fYear
1967
fDate
5/1/1967 12:00:00 AM
Firstpage
208
Lastpage
209
Abstract
A method for calculating least upper bounds on the magnitude and variance of the steady-state analogue voltage error in digital-to-analogue ladder convertors in presented. Tight bounds on the magnitude and variance of the error are calculated as a function of resistor tolerance, steady-state voltage source error and number of bits decoded.
Keywords
digital-analogue conversion; signal generators;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19670162
Filename
4207219
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