DocumentCode :
873172
Title :
A systematic methodology for the design of high performance recursive digital filters
Author :
McQuillan, Stephen E. ; McCanny, John V.
Author_Institution :
N.I. Telecommun. Eng. Centre, BNR Europe Ltd., Antrim, UK
Volume :
44
Issue :
8
fYear :
1995
fDate :
8/1/1995 12:00:00 AM
Firstpage :
971
Lastpage :
982
Abstract :
A systematic design methodology is described for the rapid derivation of VLSI architectures for implementing high performance recursive digital filters, particularly ones based on most significant digit (msd) first arithmetic. The method has been derived by undertaking theoretical investigations of msd first multiply-accumulate algorithms and by deriving important relationships governing the dependencies between circuit latency, levels of pipelining and the range and number representations of filter operands. The techniques described are general and can be applied to both bit parallel and bit serial circuits, including those based on on-line arithmetic. The method is illustrated by applying it to the design of a number of highly pipelined bit parallel IIR and wave digital filter circuits. It is shown that established architectures, which were previously designed using heuristic techniques, can be derived directly from the equations described
Keywords :
VLSI; digital arithmetic; digital filters; recursive filters; bit parallel circuits; bit serial circuits; heuristic techniques; high performance recursive digital filters; most significant digit; systematic methodology; wave digital filter circuits; Circuits; Computer architecture; Delay; Design methodology; Digital arithmetic; Digital filters; IIR filters; Pipeline processing; Signal processing algorithms; Transfer functions;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/12.403713
Filename :
403713
Link To Document :
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