An efficient noise isolation technique for SOC application

A highly efficient CMOS process technique of suppressing the transmission of high-frequency noise induced by spiral inductors, ultrafast-switching MOS gates, or supply ringing through silicon substrate has been attained. The isolated n⁺-pocket structure formed by a promising process technique designed in this work has proven to be most effective in guarding vulnerable devices from remnant high-frequency noise roaming in the substrate among the structures we have used in the experiment: p⁺ guard ring, proton implant, and pocket structures. Excellent noise suppression efficiency of -75 dB with source and sense separated by only 21 μm at 1 GHz has been achieved for the test keys with n⁺-pocket structure in contrast to -38 dB at 1GHz of unprotected devices. The isolated n⁺-pocket structure has manifested itself to possess the potential of becoming a key technology for mixed-mode circuits in future success of Si-based wireless communication system-on-chip (SOC) applications.