Title :
A 40-ns 144-bit n-channel MOS-LSI memory
Author :
Tarui, Yasuo ; Hayashi, Yutaka ; Koyanagi, Tadamasa ; Yamamoto, Hirohiko ; Shiraishi, Masamichi ; Kurosawa, Toshio
Abstract :
The analysis and characterization of a MOS random-access memory is described. An optimization technique is developed that minimizes cycle time by selection of the optimum cell dimensions for a prescribed fabrication technology. These considerations are applied to the design of a high-speed 144-bit MOS-LSI memory using n-channel devices. This memory operates with a WRITE cycle of 40-ns, which is somewhat greater than the predicted value due to the nonideal drive pulse waveform.
Keywords :
Digital storage; Large scale integration; Optimisation; Semiconductor storage devices; digital storage; large scale integration; optimisation; semiconductor storage devices; Aluminum; Capacitance; Fabrication; High speed integrated circuits; Laboratories; Large scale integration; MOSFETs; Roentgenium; Threshold voltage; Wiring;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1969.1050015
