• DocumentCode
    873944
  • Title

    A 40-ns 144-bit n-channel MOS-LSI memory

  • Author

    Tarui, Yasuo ; Hayashi, Yutaka ; Koyanagi, Tadamasa ; Yamamoto, Hirohiko ; Shiraishi, Masamichi ; Kurosawa, Toshio

  • Volume
    4
  • Issue
    5
  • fYear
    1969
  • Firstpage
    271
  • Lastpage
    279
  • Abstract
    The analysis and characterization of a MOS random-access memory is described. An optimization technique is developed that minimizes cycle time by selection of the optimum cell dimensions for a prescribed fabrication technology. These considerations are applied to the design of a high-speed 144-bit MOS-LSI memory using n-channel devices. This memory operates with a WRITE cycle of 40-ns, which is somewhat greater than the predicted value due to the nonideal drive pulse waveform.
  • Keywords
    Digital storage; Large scale integration; Optimisation; Semiconductor storage devices; digital storage; large scale integration; optimisation; semiconductor storage devices; Aluminum; Capacitance; Fabrication; High speed integrated circuits; Laboratories; Large scale integration; MOSFETs; Roentgenium; Threshold voltage; Wiring;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1969.1050015
  • Filename
    1050015
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=873944