Sensitivity analysis of a digital-by-analogue multiplier and a weighted-resistor digital-to-analogue convertor

Least upper bounds on the magnitude and variance of the analogue-voltage error in a digital-by-analogue multiplier and a weighted-resistor digital-to-analogue convertor are obtained. These bounds depend on the accuracy of the circuit components and on the number of bits multiplied or decoded. The results are applied to a practical design problem.