DocumentCode
874028
Title
Sensitivity analysis of a digital-by-analogue multiplier and a weighted-resistor digital-to-analogue convertor
Author
Donaldson, R.W.
Volume
3
Issue
10
fYear
1967
fDate
10/1/1967 12:00:00 AM
Firstpage
447
Lastpage
448
Abstract
Least upper bounds on the magnitude and variance of the analogue-voltage error in a digital-by-analogue multiplier and a weighted-resistor digital-to-analogue convertor are obtained. These bounds depend on the accuracy of the circuit components and on the number of bits multiplied or decoded. The results are applied to a practical design problem.
Keywords
analogue computers; analysis and synthesis methods; logic and computing circuits;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19670353
Filename
4207403
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