Address selection by combinatorial decoding of semiconductor memory arrays

On-chip decoding for address selection is being designed into large- capacity semiconductor memory chips to reduce the number of off-chip interconnections. A combinatorial form of decoding is offered as an alternative to the usual straight binary or selection matrix form of decoding. Combinatorial decoding circuit complexity and pad reduction, and provides an easy method of selecting a redundant line on the chip. This form of decoding uses the (/SUB m//SUP n/) combinations of n bits taken m at a time, whereas the usual binary decoding uses 2/SUP n/ combinations. Because most systems are organized in binary form, a code conversion is required to use the combinatorial form of address decoding. Since the code conversion is equivalent to a level of decoding, there is only a small logic penalty to pay.