Critical path selection for performance optimization

Author

Chen, Hsi-Chuan ; Du, David Hung-Chang ; Liu, Li-Ren

Author_Institution

Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA

Volume

12

Issue

2

fYear

1993

fDate

2/1/1993 12:00:00 AM

Firstpage

185

Lastpage

195

Abstract

The problem of selecting a set of paths to optimize the performance of a combinational circuit is studied, assuming that gate resizing and buffer insertion are the two possible optimizing techniques for reducing the delay of a circuit. The objective of the path selection problem is to select as small as possible a set of paths to ease the optimization processing to guarantee that the delay of the circuit is no longer than a given threshold τ if the delays of all the selected paths are no longer than τ. It is shown that the path selection is different from path sensitization. An input vector-oriented path selection algorithm is proposed. Because it may be infeasible for complex circuits with many primary inputs, a path-oriented algorithm is also developed and implemented. Experimental results on ISCAS85 benchmark circuits show a potentially big improvement for the optimization process

Keywords

circuit layout CAD; combinatorial circuits; critical path analysis; logic CAD; optimisation; ISCAS85 benchmark circuits; buffer insertion; combinational circuit; critical path selection; delay reduction; gate resizing; input vector-oriented path selection algorithm; optimizing techniques; path-oriented algorithm; performance optimization; Adders; Algorithm design and analysis; Circuit topology; Clocks; Combinational circuits; Computer science; Delay; Optimization; Routing; Wires;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.205000

Filename

205000