DocumentCode
874915
Title
The halo algorithm-an algorithm for hierarchical design of rule checking of VLSI circuits
Author
Hedenstierna, N. ; Jeppson, Kjell O.
Author_Institution
Dept. of Solid-State Electron., Univ. of Technol., Goteborg, Sweden
Volume
12
Issue
2
fYear
1993
fDate
2/1/1993 12:00:00 AM
Firstpage
265
Lastpage
272
Abstract
The halo algorithm, a new and efficient hierarchical algorithm for corner-based design rule checking, is presented. The basic idea is to check each cell in its context by first identifying all elements that interact with the cell, thereby completely eliminating the rechecks of the traditional hierarchical methods. Identical interactions, repeated at several instances of a cell, are identified and checked as one interaction. The concept of the inverse layout tree is introduced to handle the interacting primitives. No restrictions are enforced on the hierarchical structure of the layout, and error messages are placed in the cells where the errors should be corrected. Performance is exemplified using several test-circuits. It is shown that the halo algorithm offers a five to twentyfold speed increase when the hierarchical circuit description is verified instead of a flattened description
Keywords
VLSI; circuit layout CAD; integrated circuit technology; VLSI circuits; corner-based design rule checking; error messages; halo algorithm; hierarchical design; inverse layout tree; Algorithm design and analysis; Circuit testing; Error correction; Solid state circuits; Transistors; Very large scale integration; Wire;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.205006
Filename
205006
Link To Document