Design considerations leading to the ILLIAC IV LSI process element memories

The authors present the design considerations for a 256-bit bipolar LSI memory component and the system-packaging technology by which the LSI components were assembled to provide seventy 131 072-bit 200-ns full-cycle main process element memories for the ILLIAC IV computing system. The concepts utilized allow memory modularity from about 1024 bytes to over 3,000,000 bytes while maintaining an approximately linear price per bit over the whole range. The experience on LSI memory component and system testing is discussed. Also included are observations on experiences with component designs and prices during the PEM project.