The benefits of flexibility in lookup table-based FPGAs

FPGAs (field programmable gate arrays) need not be limited to a single fixed-size truth table in each block. The authors discuss the utility of allowing each block´s single large table (e.g. one 5-input, 32-b table) to be reconfigured into smaller tables (e.g. eight 4-b tables). Results describing the efficiency of packing some standard benchmark circuits into various configurations are presented and the cost/benefits discussed. It is shown that a logic block containing four lookup tables, each of which is 8-b RAM, is the best choice if only the area efficiency is considered. It is also shown that if circuit speed is considered, a logic block containing two lookup tables, each of which contains 16 b of RAM, is the best choice