• DocumentCode
    876151
  • Title

    Timing modeling and optimization under the transmission line model

  • Author

    Chen, Tai-Chen ; Pan, Song-Ra ; Chang, Yao-Wen

  • Author_Institution
    Graduate Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan
  • Volume
    12
  • Issue
    1
  • fYear
    2004
  • Firstpage
    28
  • Lastpage
    41
  • Abstract
    As the operating frequency increases to gigahertz and the rise time of a signal is less than or comparable to the time-of-flight delay of a wire, it is necessary to consider the transmission line behavior for delay computation. We present in this paper, an analytical formula for the delay computation under the transmission line model. Extensive simulations with SPICE show the high fidelity of the formula. Compared with previous works, our model leads to smaller average errors in delay estimation. Based on this formula, we show the property that the minimum delay for a transmission line with reflection occurs when the number of round trips is minimized (i.e., equals one). Besides, we show that the delay of a circuit path is a posynomial function in wire and buffer sizes, implying that a local optimum is equal to the global optimum. Thus, we can apply any efficient search algorithm such as the well-known gradient search procedure to compute the globally optimal solution. Experimental results show that simultaneous wire and buffer sizing is very effective for performance optimization under the transmission line model.
  • Keywords
    SPICE; delay estimation; gradient methods; integrated circuit interconnections; optimisation; search problems; transmission line theory; SPICE; buffer sizing; delay computation; delay estimation; gigahertz; gradient search; interconnection lines; optimization; posynomial function; search algorithm; time-of-flight delay; timing modeling; transmission line model; wire sizing; Computational modeling; Delay effects; Delay estimation; Delay lines; Distributed parameter circuits; Frequency; SPICE; Timing; Transmission lines; Wire;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2003.820529
  • Filename
    1263556