A stability criterion for high-accuracy Δ-Σ digital resonators

While microelectronic companies are increasingly focused on the production of system on chips (SoCs) comprising both analog and digital sections, the expenses related to the test of high-density mixed-signal chips have become the main cost factor due to the long testing time and the need for complex automated test equipment (ATE). Built-in self-test (BIST) techniques represent an effective solution to tackle this problem, as they rely on the integration of testing-oriented resources on the same chip to be tested. Among all the possible circuits to be used for BIST purposes, simple and high-purity harmonic resonators are essential to perform an accurate characterization of analog-to-digital converters (ADCs). In particular, Δ-Σ harmonic resonators are very suitable for BIST schemes, but they have proved to be critically stable and difficult to implement due to the lack of clear design criteria. In this paper, a general method to analyze the behavior of Δ-Σ harmonic resonators is presented. The proposed criterion suggests some guidelines to implement more stable and robust resonators.