Title :
A low-temperature MOS LSI process
Author :
Hashimoto, Chisato ; Ushizaka, Hironori
Author_Institution :
Electr. Commun. Labs., NTT, Atsugi, Japan
fDate :
3/1/1988 12:00:00 AM
Abstract :
A low-temperature process is proposed for the fabrication of MOS LSIs with very small dimensions. Since this process needs no thermal treatment after gate insulation, shallow source/drain junction, ultra-thin gate oxide, and Al gate electrode can be used. The key processes are self-aligned gate pattern reversion using Mo dummy gates and ECR SiO/sub 2/ lift-off, and planarized Al gate electrode filling using resist/Al etch-back. Test devices fabricated to demonstrate the feasibility of this process operate without trouble.<>
Keywords :
field effect integrated circuits; integrated circuit technology; large scale integration; Al-SiO/sub 2/-Si; MOS LSI process; dummy gates; electrode filling; feasibility; gate electrode; lift-off; low-temperature process; self-aligned gate pattern reversion; shallow source/drain junction; ultra-thin gate oxide; Annealing; Artificial intelligence; Electrodes; Etching; Fabrication; Filling; Insulation; Large scale integration; Plasma temperature; Resists;
Journal_Title :
Electron Device Letters, IEEE
