Radiation Test Challenges for Scaled Commercial Memories

Author

LaBel, Kenneth A. ; Ladbury, Ray L. ; Cohn, Lewis M. ; Oldham, Timothy R.

Author_Institution

Goddard Space Flight Center, NASA, Greenbelt, MD

Volume

55

Issue

4

fYear

2008

Firstpage

2174

Lastpage

2180

Abstract

As sub-100 nm CMOS technologies gather interest, the radiation effects performance of these technologies provide a significant challenge. In this paper, we shall discuss the radiation testing challenges as related to commercial memory devices. The focus will be on complex test and failure modes emerging in state-of-the-art flash non-volatile memories (NVMs) and synchronous dynamic random access memories (SDRAMs), which are volatile. Due to their very high bit density, these device types are highly desirable for use in the natural space environment. In this paper, we shall discuss these devices with emphasis on considerations for test and qualification methods required.

Keywords

CMOS memory circuits; DRAM chips; failure analysis; flash memories; integrated circuit testing; radiation hardening (electronics); CMOS technology; failure modes; memory devices; radiation effects; radiation testing; state-of-the-art flash nonvolatile memory; synchronous dynamic random access memory; CMOS technology; Field programmable gate arrays; Materials testing; NASA; Nonvolatile memory; Packaging; Qualifications; Radiation effects; SDRAM; Space technology; CMOS; commercial memories; radiation effects;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2008.2001481

Filename

4636934