An Efficient Rasterization Unit With Ladder Start Tile Traversal in 3-D Graphics Systems

To render 3-D graphics efficiently, rasterization techniques have been developed. Traditional triangle traversal techniques using scan-line-based or edge-equation-based methods may cause potential instability from the division operations. This paper develops an efficient rasterization algorithm-a barycentric-based ladder start tile traversal that is division free. Throughout the process, no extra traversal position and context is produced to reduce the number of pixel tests and improve the efficiency and stability of the graphic rendering. It also presents the architecture of a 300 MHz 3-D graphics rasterizer in a 65 nm 1P9M process with a core size of 0.537 mm(^{2}) and internal buffer 3 K. The proposed ladder start tile traversal architecture can perform each tile intersect test in six cycles and tile interior traversal with barycentric tests in 2 pixels per cycle. In addition, the rasterizer throughput can achieve up to 50M triangles per second and 600M pixels per second.