Title :
A dynamic delay line with a bipolar one-transistor cell
Author :
Kasperkovitz, D.
Abstract :
A new bipolar one-transistor cell for the storage of analog information is described. This cell forms the basis of a 256-sample dynamic delay line, where 16/spl times/16 cells of a two-dimensional array are successively accessed. The circuitry for the generation of the selection voltages is specially designed in order to make the power dissipation independent of the size of the delay line.
Keywords :
Analogue storage; Bipolar transistors; Delay lines; Random-access storage; Semiconductor storage devices; analogue storage; bipolar transistors; delay lines; random-access storage; semiconductor storage devices; Capacitance; Charge coupled devices; Charge transfer; Circuits; Delay effects; Delay lines; Power dissipation; Power generation; Voltage; Writing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1973.1050393
