Design of high-speed bipolar flip-flops for reduced clock loading

A new topology for flip-flops is presented. A current amplifier is incorporated into a standard, current mode logic, D-type flip-flop. The gain cell effectively buffers the clock without requiring additional current. Level shifting emitter followers from the clock are reduced in size and current. The frequency response of the gain cell selectively applies a keep-alive current to the circuit at high frequency without distorting low frequency outputs. The flip-flop is configured as a static frequency divider and compared to a standard flip-flop in a bipolar SiGe process. The new circuit is faster and requires less clock power at high frequency, making it suitable for large-scale integration.