Design of Schottky-barrier diode clamped transistor layouts

Describes an approach to the design of Schottky-clamped integrated circuit transistor layouts. Three-dimensional distributed resistances are modeled using a grid of lumped resistors. A computer circuit analysis program is used to obtain a simple lumped equivalent circuit for the clamped transistor. The equivalent circuit enables accurate prediction of the useful range of d.c. operating conditions for a given structure. An improved small-area clamped transistor layout has been developed using this approach.