Title :
Area-efficient correlated double sampling scheme with single sampling capacitor for CMOS image sensors
Author :
Han, S.-W. ; Yoon, E.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejon, South Korea
fDate :
3/16/2006 12:00:00 AM
Abstract :
An area-efficient correlated double sampling (CDS) circuit is proposed. In conventional designs, most of the area of CDS circuits is occupied by two large on-chip sampling capacitors. A new CDS scheme is devised using only one sampling capacitor. The proposed CDS circuit has been successfully realised in a small two column pitch of 7.2 μm in a test chip fabricated using 0.18 μm CMOS process and has demonstrated fixed pattern noise less than 0.46%.
Keywords :
CMOS image sensors; analogue-digital conversion; capacitors; integrated circuit noise; 0.18 micron; CMOS image sensor; area-efficient correlated double sampling circuit; circuit design; column pitch; fixed pattern noise; single sampling capacitor; test chip fabrication;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20064189
