• DocumentCode
    878206
  • Title

    Accurate metallization capacitances for integrated circuits and packages

  • Author

    Ruehli, Albert E. ; Brennan, Pierce A.

  • Volume
    8
  • Issue
    4
  • fYear
    1973
  • Firstpage
    289
  • Lastpage
    290
  • Abstract
    The parallel-plate formula is widely used by the solid-state circuit designer to estimate capacitances in integrated circuits. Since considerable errors may result from using this approximation, this correspondence gives correction curves for a wide range of parameters. It is shown that the finite conductor thickness may significantly contribute to the increase in capacitance.
  • Keywords
    Capacitance; Metallisation; Monolithic integrated circuits; Packaging; capacitance; metallisation; monolithic integrated circuits; packaging; Capacitance; Conductors; Delay; Dielectric substrates; Error correction; Integrated circuit metallization; Integrated circuit packaging; Permittivity; Switching circuits; Upper bound;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1973.1050400
  • Filename
    1050400
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=878206