Computer-aided analysis of solid-state analog delay lines using conventional circuit analysis programs

A method is described for analyzing the two-dimensional behavior of minority carriers in a solid-state analog delay line by applying, without modification, existing computer-aided circuit analysis programs to a lumped model. Development of the model in two dimensions is based on an approximate solution of the minority carrier partial differential equation using an analogous electrical network. The model includes injecting and collecting junction nonlinearities and thereby permits the study of responses to arbitrary external excitations. Several examples of the use of the model are given.