Title :
High performance MOS integrated circuit using the ion implantation technique
Author :
Fang, Frank F. ; Rupprecht, Hans S.
fDate :
8/1/1975 12:00:00 AM
Abstract :
Extensive use has been made of the advantages ion implantation has to offer over standard processing for the fabrication of high performance n-channel MOS circuits. By combining an enhancement driver with a depletion load, the maximum switching speed of FET logic elements has been evaluated for self-aligned structures with various channel lengths and various degrees of substrate decoupling via device-to-substrate capacitances. An 11-stage ring-oscillator circuit is used for performance evaluation. Switching delays as small as 115 ps were obtained for such inverter stages built on 200 Ω×cm substrate material and having 1-μm channel length. Essential fabrication details and circuit behaviors are described.
Keywords :
Digital integrated circuits; Integrated circuit production; Ion implantation; Logic circuits; Monolithic integrated circuits; digital integrated circuits; integrated circuit production; ion implantation; logic circuits; monolithic integrated circuits; FETs; Fabrication; Inverters; Ion implantation; Logic devices; MOS integrated circuits; MOSFET circuits; Parasitic capacitance; Semiconductor impurities; Substrates;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1975.1050595
